Corentin wins Best Dissertation Award

Corentin wins Best Dissertation Award

I am pleased to share that my (now former) student, Dr. Corentin Pochet, received the 2023-2024 Dr. William S.C. Chang Best Dissertation Award for his thesis titled “Higher-order VCO-based ADCs for Sensor Interfaces!” In his thesis, Corentin describes several innovations at the circuit and architecture level that can increase the noise-shaping order of a VCO-based ADC and achieve outstanding linearity. These techniques are implemented in two chips that he taped out.

The first ADC was designed to interface directly with high-impedance recording electrodes and provide a wide dynamic range and linearity to absorb motion artifacts and correct them in the digital domain. The prototype ADC achieves 2nd-order noise-shaping with high linearity and power efficiency using a novel gated inverted ring oscillator (GIRO)-based time-to-digital converter and a multi-quantizer scheme. The ADC achieves a dynamic range greater than 90 dB and above 110 dB of linearity while consuming only 5.4 µW of power! This was published in ISSCC and subsequently invited to TBioCAS.

The second prototype was developed by building upon the feedforwarding techniques commonly used in the standard voltage domain ADC architectures and applying them to capacitively coupled VCO-based ADCs. Using the pseudo-virtual ground (PVG) at the input of the VCO integrator and feeding it further down the loop, he showed that high linearity and higher-order noise-shaping shaping could be achieved extremely power-efficiently. The prototype achieved 3rd-order noise-shaping with a 92.1 dB SNDR and a peak linearity of 123 dB while consuming only 4.4 µW. This led to a Schreier FoM of 179.6 dB, indicating how efficient the proposed structure is and showing comparable performance to standard voltage domain architectures. This was published in ISSCC and subsequently invited to JSSC.

To better contextualize his work, I refer you to the plots below. These plots show the landscape of ADC performance over the past 25+ years, comparing the Schreier FoM versus the conversion rate (fs,nyq) of the ADC, where a higher FoM indicates higher performance. When Corentin started his PhD, there was a 20 dB gap between the best-performing voltage-mode ADCs and the best VCO-based ADCs. Throughout his thesis, he closed this gap to less than 4 dB and (shhh….) recently taped out a chip that is even better than all voltage-mode ADCs. Corentin’s works are circled.

State-of-the-art ADCs in 2016

State-of-the-art ADCs in 2022

Omid to present at VLSI 2022

I am excited to report that our paper, “Helix: An Electrochemical CMOS DNA Synthesizer,” will be presented tomorrow at VLSI in Honolulu by Omid! This was a multi-year collaborative effort with Avery Digital to demonstrate high-density DNA synthesis atop a CMOS chip. We developed a new low-voltage redox chemistry, implemented post-processing techniques for high-density platinum electrodes (as small as 0.6μm2), and synthesized oligos up to 100 nucleotides. Come check out the exciting talk!

Corentin to present at ISSCC 2022

Corentin will present his work titled “A 4.4µW, 2.5kHz-BW, 92.1dB-SNDR 3rd-Order VCO-based ADC with Pseudo Virtual Ground Feedforward Linearization” at ISSCC this year! This work shows how one can feed forward the pseudo virtual ground in a capacitively coupled VCO-based ADC to linearize and stabilize the system while only using a single feedback DAC. This approach enables a high dynamic range (DR) due to the 3rd-order noise-shaping and >120dB SFDR due to the linearization. The prototype ADC consumes 4.4µW from a 0.8V supply achieving the best-reported SNDR Schreier Figure-of-Merit (FoM) for VCO-based ADCs at 179.6dB.

Congratulations, Corentin!

Corentin to present at ISSCC 2021

Come check out our ISSCC paper, #28.4 titled “A 400mVpp 92.3dB-SNDR 1kHz-BW 2nd-Order VCO-Based ExG-to-Digital Front-End Using a Multiphase Gated-Inverted Ring-Oscillator Quantizer.” Corentin will describe a second-order VCO-only delta-sigma ADC with a wide dynamic range (>90dB) and a high input impedance (>50MΩ) enabling the direct digitization of ExG signals even in the presence of large motion artifacts while consuming less than 6μW. Great work from Corentin Pochet, Jiannan(Jason) Huang, and Patrick Mercier!

Somok to present at ISSCC 2021

Come check out our ISSCC paper, #10.2 titled “A 139μW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking and FIR DACs”. Somok will present our work on “OTA-Stacking” to improve the noise efficiency of circuits. Having already shown the benefit of this technique in an ultra-low power ECG amplifier, we demonstrate how this can be used in an analog-to-digital converter (ADC) with state-of-the-art performance. Congrats, Somok Mondal and Omid Ghadami! Also, a post on the JSOE blog here.